International Conference on IC Design and Technology

Tutorial Program

Tutorial Program

The whole day on Wednesday, May 29th, 2013 is devoted to tutorials. The tutorial program is the following:

09:30–10:30 – Tutorial 1

Trends in Power Semiconductors for Energy Efficient Applications

Dr. Marnix Tack, ON Semiconductors, Belgium

This tutorial will give an overview of the landscape and the trends in the field of power semiconductors, covering technologies such as power system-on-chip (SoC) “smart power,” high voltage/high power discrete (both Si and wide-band-gap), and high power modules.  It will be demonstrated that the main drivers for technological innovation are energy efficiency and cost at both the component and system level.  This drives technology innovations for higher performance at increased switching frequency and increased integration level (“smart” systems), resulting in higher functionality at reduced footprint/weight, reduced power loss, and reduced heating at an affordable cost.  Examples will be given for automotive applications, including Ecar, and computing applications.

Marnix Tack received the M.Sc. degree in electrical engineering from the University of Gent, Belgium, in 1984, and the Ph.D. degree from the Catholic University of Leuven, Belgium in 1991.  He joined IMEC in 1985 working in the field of SOI-CMOS.  He joined Mietec in 1990, now ON Semiconductor.  He held several technical and management positions, managing programs and teams working on CMOS, SiGe-BiCMOS, NVM, BCD, and discrete power technologies.  Dr. Tack is presently Senior Director of the Power Technology Centre within ON, that is developing innovative smart power and discrete high voltage and power technologies, both in Si and GaN.  He (co-)authored over 70 publications and holds several patents.

11:00–12:00 – Tutorial 2

Silicon Photonics: An Industrial Perspective Enabling Low Cost Volume Applications

Dr. Guido Chiaretti, STMicroelectronics, Italy

After the first research done on the integration of photonics in silicon up to the first years of 2000, a huge work has been done worldwide with the R&D contribution of the most important industrial laboratories, like Intel, IBM, and HP for example, and many research centers.  A summary of the art in this field will be given and the basic reasons of this effort will be presented and discussed.  Today, Silicon Photonics is becoming a mature technology, but a lot of work has still to be done on the technological side and industrial strategy.  The tutorial will also review the real advantages, some limitations, and trade-offs that a circuit designer must have clear in mind to be effective in proposing a certain solution based on Silicon Photonics.  An overview of foreseen applications for which Silicon Photonics is beneficial will conclude the tutorial.

Guido Chiaretti graduated in Physics at the University of Milan, Italy in 1976.  Presently, he is Director of New Technologies inside the R&D of the Imaging, Bi-CMOS ASIC & Silicon Photonics Group of STMicroelectronics located in Milan, Italy.  He introduced Silicon Photonics in ST in the last seven years.  He joined ST with his R&D group in 2000 bringing the Planar Lightwave Circuit (PLC) technology to develop a 32x32 optical matrix switch.  From 1980 to 2000, he was the head of the Photonic Unit in the Central R&D of Italtel, where he jointly developed PLC technology with AT&T Bell Labs in early 1990’s.  Previously, he was also active in R&D of Optical fiber Communication, Free Space Communication, Plastic Optical Fiber Links for Automotive applications, designing many micro-optic or discrete, active or passive optical devices.  From 1977 to early 1980’s, he was designer of semiconductor LED and Laser sources operating in first, second, and third window on Optical Fibers.

13:30–14:30 – Tutorial 3

Defect-Centric Perspective of Device Reliability

Dr. Ben Kaczer, IMEC, Belgium

In the deeply downscaled CMOS devices with ~10 nm gate lengths, only a handful of defects will be present in each device, while their relative impact on the device characteristics will be significant.  The defect behavior is stochastic, voltage and temperature dependent, and widely distributed in time, resulting in each device behaving very differently during operation.  We will show how the physical properties of individual defects can be understood, described, and propagated to higher design abstraction levels to project device and circuit lifetime distributions.

Ben Kaczer is a Principal Scientist at IMEC, Belgium.  He received the M.S. degree in Physical Electronics from Charles University, Prague, in 1992 and the M.S. and Ph.D. degrees in Physics from The Ohio State University, in 1996 and 1998, respectively.  In 1998, he joined the reliability group of IMEC.  He has co-authored more than 300 journal and conference papers, presented a number of invited papers and tutorials at international conferences, and received 5 IEEE IRPS Best or Outstanding Paper Awards, an IEEE IPFA Best Paper Award, and the 2011 IEEE EDS Paul Rappaport Award.  He has served or is serving at various functions at the IEDM, IRPS, SISC, INFOS, and WoDiM conferences.  He is currently serving on the IEEE T. Electron Dev. Editorial Board.

15:00–16:00 – Tutorial 4

From Device to Product Reliability – A Modeling Value Chain

Dr. Vincent Huard, STMicroelectronics, Belgium

For many decades, IC component reliability relies on a top-down approach.  In this approach, various elements of the product’s mission profile were translated into reliability specifications at the component level.  Nevertheless, this approach presents limitations in generating reliability specifications for the IPs or elementary blocks of the component.  These limitations become even more important to overwhelm with the continuous technology scaling and its related increase of the reliability impact.  For that purpose, lots of RnD works have been published over the last years regarding a bottom-up approach.  In this approach, the reliability is dealt at design level from the beginning.  In a first time, the top-down approach and its limitations will be reviewed.  From that status, this tutorial will introduce the bottom-up approach and will provide the key elements (and related examples) to focus on to design and qualify products accordingly to a Design for Reliability (DFR) flow.

Vincent Huard received the B.S. (1996) in physics and the M.S. (1997) in electrical engineering from the Institut National Polytechnique de Grenoble (INPG).  He worked for the CEA-Grenoble on the MBE growth of II-VI based doped heterostructures and their magneto-optical and electrical characterizations.  He received his Ph.D. (2000) in physics from the University of Grenoble.  In 2000 and 2001, he was a Visiting Scholar at the University of California, where he worked on devices made of ferromagnetic materials on top of semiconductors.  In 2002, he joined Philips Semiconductors as a reliability engineer, working on oxide and device reliability.  Since 2007, he is at STMicroelectronics, now serving as Device to Product Reliability manager, working on device and circuit reliability modeling and product qualification tests.  His current research interests include NBTI, HCI and TDDB degradations both at wafer and product levels as well as design for reliability.  He authored and co-authored more than 140 regular papers, several invited papers and tutorials, held 9 patents and is serving as IRPS Management Committee member.